A High performance OC OC Queue Design Prototype for Input bu ered ATM Switches

This paper presents the design and prototype of an intelligent Dimensional Queue DQ for high performance scalable input bu ered ATM switches DQ uses pointers and linked lists to organize ATM cells into multiple virtual queues according to prior ity destination and virtual connection It enforces per virtual connection Quality of Service QoS and elim inates Head Of Line HOL blocking Using Field Programmable Gate Array FPGA devices our proto type hardware can process ATM cells at Mb s OC Using more aggressive technology Multi Chip Module MCM and fast GaAs logic the same DQ design can process cells at Gb s OC Using DQ and Matrix Unit Cell Scheduler MUCS as essen tial components an input bu ered ATM switch system has been designed which can achieve near link bandwidth utilization Introduction The queuing strategies of ATM switches can be broadly classi ed as input queuing IQ output queuing OQ or shared memory SM Combining two of the above results in input output queuing IOQ input shared queuing ISQ or output shared queuing OSQ Of all queuing con gurations the IQ structure requires the least memory bandwidth for bu ering ATM cells Each queue module of an IQ switch only bu ers cells at the arrival rate of a single port rather than at a multiple of the arrival rate as with other structures In addition it has been found through simulation that with the same bu er size an IQ switch has more tolerance for bursty tra c Moreover for multicast tra c a burst of n cells that are to be deliv ered to m output ports only needs n cell bu ers for the This research has been supported by National Science Foun dation Engineering Research Center grant ECD Ad vance Research Program Agency ARPA grant for Center for Optoelectronic Science and Technology COST grant MDA IQ structure rather than m n cell bu ers for the OQ structure Therefore IQ is well suited to meet the re quirements of current and future ultra broadband ATM networks We have successfully implemented a prototype port input bu ered ATM switch system using FPGA devices for our ATM network testbed the iPOINT Illinois Pulsar based Optical Interconnect The sys tem was fully functional and provided an aggregate throughput of Mb s The First In First Out FIFO queue implementa tion used in the previous testbed su ered from HOL blocking and QoS enforcement Our second generation iPOINT input queuing ATM switch as illustrated in Figure uses a non FIFO Dimensional Queue DQ for cell bu ering DQ avoids HOL blocking by bu er ing ATM cells in a Random Access Memory RAM and organizing them into multiple virtual queues Cells are selected for transmission based on Quality of Service QoS parameters of their virtual connections and run time tra c conditions Matrix Unit Cell Scheduler (MUCS) N x N NonBlocking Fabric Switch local scheduling RAM